Wafer Level Chip Scale Packaging (WLCSP) is the most compact package footprint having improved thermal and electrical performance over wirebond and other interposer packaging technologies. FIG. 1 illustrates a WLCSP structure including a redistribution layer (RDL) 18 contacting a metal pad 12 on a silicon wafer 10 through an opening in a first polymer layer 16. An under bump metal (UBM) layer 22 is formed contacting the RDL 18 through an opening in second polymer layer 20. Solder ball 24 is placed onto the UBM.
Many Outsourced Assembly and Test (OSAT) have adapted Polybenzobisoxazole (PBO) as the primary polymer passivation material for 300 mm diameter wafers. PBO (HD8820) was believed to be earth-friendly using an aqueous developer as opposed to a solvent and having a better stress buffering property than polyimide (PI). However, discoloration and delamination at the RDL/second polymer interface has been detected on a WLCSP device during early reliability testing. In power management devices, there is a very high RDL metal density (i.e. >55-75% of the die area) for better electrical and thermal performance. With such a high RDL metal density, adhesion problems between PBO and the RDL are more likely.
U.S. Pat. No. 7,384,822 (Zacherl et al) and U.S. Pat. No. 9,633,837 (Raghunathan et al) discuss adhesion between dielectric and conductor layers in a semiconductor package.